This application is related to the following U.S. patent applications filed on even date herewith: xe2x80x9cMETHOD FOR PROVIDING DUAL WORKFUNCTION DOPING AND PROTECTIVE INSULATING CAPxe2x80x9d, Ser. No. 09/325,941, filed Jun. 4, 1999, and xe2x80x9cMETHOD AND APPARATUS FOR PROVIDING LOW-GIDL DUAL WORKFUNCTION GATE DOPING WITH BORDERLESS DIFFUSION CONTACTxe2x80x9d, Ser. No. 09/325,943, filed Jun. 4, 1999 the Specifications of which are incorporated herein by reference.
This invention relates to a method of forming semiconductor devices and, more particularly, to modified gate conductor processing for polysilicon length control in high density dynamic random access memories or embedded memories.
The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow for continued cell shrinkage with only limited shrinking of the channel length.
As the DRAM cell size has decreased, the transfer gate has consequently shrunk with it. Earlier cell sizes ( greater than 8F2) allowed for wiggled gates to keep the array transistor off leakage to a minimum. With the onset of 8F2 cells with equal lines and spaces at minimum F in the wordline direction, there is a need to provide for larger transfer gate lengths of the array pass transistor by non-lithographic techniques. Conventional scaling techniques use shallow junctions (limited by surface leakage and charge writeback characteristics), high channel doping concentrations or halo implants which increase leakage and are thus not easy to incorporate in a DRAM process.
One known process is based on the BEST (BuriEd Strap) cell modified for 8F2. Once the trench capacitor and shallow trench isolation is formed the gate stack is put down. Typically, the gate stack consists of polysilicon and WSix capped with SiN. During the gate mask open step, the SiN is patterned and the etch typically stops in the WSix, the resist is stripped and the remaining stack etched with the SiN as the hardmask. Post gate sidewall oxidation, the SiN spacers are put down followed by a barrier SiN film and BPSG deposition, densification and planarization. A TEOS layer is put down for the damascene bitlines and the bitline contacts are etched borderless to the gates before putting down the bitline wiring layer (generally tungsten).
The present invention is directed to further improvements in gate conductor processing.
In accordance with the invention, gate conductor processing is modified to control polysilicon length.
In accordance with one aspect of the invention, the process prevents anomalous tungsten silicide oxidation and straightening of tungsten silicide profile for improved array gap fill.
In accordance with a further aspect of the invention, the process allows for thinning of a layer of tungsten silicide by making it more tungsten rich.
In accordance with yet another aspect of the invention, the process allows for modulation of polysilicon length.
In accordance with still a further aspect of the invention, the process increases margins for borderless contact etch.
Broadly, there is disclosed herein the process of forming a semiconductor device comprising the steps of providing a semiconductor substrate having a gate dielectric thereon; forming a gate stack on the gate dielectric, the gate stack including a lower layer, and an upper layer on the lower layer; etching the upper layer completely through to the lower layer to provide a gate conductor, with the lower layer having a length greater than a length of the upper layer; and forming spacers on sidewalls of the upper layer substantially flush with the sidewalls of the lower layer.
More particularly, there is disclosed herein the process of forming a semiconductor device comprising the steps of providing a semiconductor substrate having an oxide layer thereon; forming a gate stack on the oxide layer, the gate stack including a layer of polysilicon on the oxide layer, a gate conductor material layer on the polysilicon layer, and a nitride cap layer on the gate conductor material layer; mask open etching the gate stack by patterning the nitride cap layer and etching completely through the tungsten silicide layer to provide a gate conductor; forming dielectric spacers on the gate conductor overlaying the nitride cap layer and the tungsten silicide layer; and etching the polysilicon layer forming vertical sidewalls substantially flush with the spacers to provide gate conductor sidewalls extending to the oxide layer.
It is a feature of the invention that thickness of the spacers is modulated to vary thickness of the polysilicon layer underneath.
It is another feature of the invention that the gate conductor material is a tungsten silicide layer that is relatively tungsten rich to reduce thickness of the tungsten silicide layer or lower the gate resistivity for the same thickness.
It is an additional feature of the invention that the spacers prevent anomalous gate conductor material oxidation.
It is still another feature of the invention that the gate conductor material is selected from a group consisting of tungsten silicide, tungsten nitride, tantalum silicide, tantalum silicon nitride or combinations thereof.
It is a further feature of the invention that the spacers provide straightening of the gate conductor material layer profile.
It is yet another feature of the invention that the forming step includes forming a barrier layer between the polysilicon layer and the gate conductor material layer. The barrier layer is selected from a group consisting of TiN, WN, TaSi2 and TaSiN.
It is yet an additional feature of the invention that the forming step comprises depositing a layer of dielectric material over the polysilicon layer and the gate conductor. The dielectric material is selected from a group consisting of nitride, oxide, TEOS or doped oxides like ASG, BSG, PSG or BPSG. The horizontal surfaces of the dielectric layer are etched to form the spacers.
In accordance with another aspect of the invention there is disclosed a semiconductor device including a semiconductor substrate having a gate dielectric thereon. A gate conductor is provided on the gate dielectric, the gate conductor including a lower layer and an upper layer on the lower layer. The lower layer has a length greater than length of the upper layer. Spacers on sidewalls of the upper layer are substantially flush with sidewalls of the lower layer.
In accordance with still another aspect of the invention there is disclosed a semiconductor device including a semiconductor substrate having an oxide layer thereon. A gate conductor is provided on the oxide layer, the gate conductor including a layer of polysilicon on the oxide layer, a tungsten silicide layer on the polysilicon layer, and a nitride cap layer on the tungsten silicide layer. The polysilicon layer has a length greater than length of the silicide layer and the nitride layer. Dielectric spacers on the gate conductor overlay the nitride cap layer and the tungsten silicide layer to provide a sidewall substantially flush with the polysilicon layer. Exposed polysilicon on the polysilicon layer is oxidized.
More particularly, the invention relates to a process integration technique which allows for a larger gate polysilicon length for a given pitch, thus improving array device leakage (by about one generation) for a given technology. This novel integration technique allows for a larger array pass transistor length. The channel length of the pass transistor is increased by the use of SiN xe2x80x9cprespacersxe2x80x9d which are spacers formed before the gate polysilicon is etched. This allows for a large array polysilicon length without sacrificing the borderless bitline contact.
The modified process exercised on a 175 nm 8F2 cell is similar to the standard process until the gate mask open step, which is modified to etch completely through the WSix. The resist is stripped and the WSix is annealed at about 800xc2x0 C. SiN spacers are formed on the sidewall and then the polysilicon is etched. The gate sidewalls are then oxidized.
The single biggest advantage of the modified process described above is the increased gate length in the array. Increased gate length results in a tighter threshold voltage distribution and thus increased stored charge. In addition it is to be noted that since the WSix is encapsulated in SiN and is not exposed to the oxidation, a W rich silicide or metal gate is used which allows for a lower gate sheet resistance. The WSix anneal is needed after the mask open step to prevent anomalous WSix oxidation which can occur in its absence during the SiN deposition.